Adiuvo Engineering представила бюджетную плату разработки FPGA за 99 долларов с чипом AMD

If you’re looking for a real bargain in an FPGA development board, Adiuvo Engineering’s Adam Taylor has a deal for you. His company’s new $99 Explorer dev board sports an AMD Artix UltraScale+ AU7P FPGA, which is lower than the single-piece price for the FPGA alone. How does Adiuvo work this magic? AMD was an active participant in this board’s development because it wanted a low-cost dev board for the Artix UltraScale+ family. Taylor’s Adiuvo was willing to put in the grunt work to make the board a reality. As with any FPGA dev board, the Artix UltraScale+ AU7P FPGA’s feature set largely defines the board’s capabilities, so it’s worth looking at the device’s spec sheet first, then we’ll look at how those specs are realized on the Explorer board. The Adiuvo Explorer dev board incorporates an AMD Artix UltraScale+ AU7P FPGA and makes most of the FPGA’s features available on several I/O connectors including four PMOD ports and two SYZYGY ports. Image credit: Adiuvo Engineering Xilinx announced its 16nm UltraScale+ FPGAs more than a decade ago. The Artix subfamily was the original low-end, er, excuse me, “cost-effective” subfamily. Then, in 2024, after AMD had purchased Xilinx, the company finally introduced the Spartan UltraScale+ family, somewhat muddling the UltraScale+ family’s low-end story. Specs for the Artix UltraScale+ AU7P FPGA appear below. Ignoring the marketing math that created the System Logic Cells “specification,” AMD’s AU7P FPGA provides the designer with 75K flip-flops, 37K LUTs, 108 Block RAM (BRAM) blocks with 36kbits per block, 216 DSP slices, and four 12.5Gbps GTH serial transceivers. In Adam Taylor’s words, “That is a genuinely capable device for signal processing, embedded acceleration, and communications work, and it is the smallest member of a family that scales up considerably if a design later needs to grow.” For a low-cost FPGA, an Artix UltraScale+ Au7P FPGA provides plenty of resources for a system design. Image credit: AMD The largest member of the Artix UltraScale+ FPGA family provides 282K flip-flops, 141K LUTs, 300 Block RAM (BRAM) blocks with 36kbits per block, 1200 DSP slices, and twelve 16.3Gbps GTY serial transceivers. That’s a serious leap in capabilities based on the same basic FPGA architecture, should your project needs grow. Because the Artix subfamily is at the low end of the UltraScale+ FPGA family, there’s even more room to grow within the same architecture and tool set using AMD’s Kintex and Virtex UltraScale+ FPGAs. Speaking of tool sets, this is a good place to talk about the MicroBlaze V soft-core microprocessor that you can drop into an AMD FPGA. In my experience, approximately 99.999% of all new FPGA-based designs need a microprocessor, and in the AMD FPGA chrono-synclastic infundibulum, that’s likely to be a MicroBlaze core. If the name “MicroBlaze” makes you think of an old, proprietary processor architecture, you’re seriously out of date. The MicroBlaze V soft core is AMD’s implementation of the open-source RISC V 32-bit microprocessor architecture with the base instruction set plus the optional multiplication/division (M), atomic (A), floating-point (F), code-compression (C), and bit-manipulation (ZBa, ZBb, ZBc, and ZBs) instruction extensions. There’s broad and growing worldwide support for RISC V software development, which includes the tools provided by AMD’s Vivado Design Suite. Vivado is AMD’s main FPGA development tool suite. Adiuvo’s $99 Explorer dev board includes a Vivado license. I expect that AMD will add a board support package for Adiuvo’s Explorer board in the future. Adiuvo itself plans to provide additional support software for the Explorer board including power-management software and sample code. With its 216 DSP48E2 DSP slices, the AU7P FPGA makes a formidable DSP engine. Each DSP slice includes a 27×18-bit multiplier and a 48-bit accumulator. In aggregate, that’s plenty of DSP horsepower. It’s the sort of DSP computing ability that put standalone DSPs out of business. Taylor has a deep interest in DSP applications for FPGAs, so you can expect that he will be developing sample DSP code and tutorials for the Artix UltraScale+ AU7P’s DSP capabilities. Adiuvo’s Explorer dev board directly implements several of the Artix UltraScale+ FPGA’s I/O capabilities as board-level features including four PMOD connectors that implement Digilent’s PMOD I/O standard, which is primarily used for external sensors, displays, and actuators. Many hardware vendors, including Digilent, offer a multitude of low-cost PMOD modules, which are very handy for system development. Two more connectors on the Adiuvo Explorer dev board implement Opal Kelly’s SYZYGY and Digilent’s Zmod high-speed serial interfaces. These serial interfaces support applications including high-speed data acquisition, machine vision, HDMI, and software-defined radio. An on-board USB C connector serves as the board’s power port, programming port, and JTAG debug port. The Explorer board also has an on-board Raspberry Pi RP2040 microcontroller, which Adiuvo uses for power management and to implement some SYZYGY features. You might be able to harness part of the RP2040 for your own purposes, but because the board uses the RP2040 for power management, you mess with it at your own risk. The Artix UltraScale+ AU7P is packaged in an FCVA289 BGA with a 0.5mm pitch. Conventional PCB design methodology says that fine-pitch packages require a High Density Interconnect (HDI) design methodology with blind and buried vias, which are cost-prohibitive for a low-cost board like the Adiuvo Explorer. Consequently, Taylor expended a lot of effort on signal-integrity and power-integrity simulations to allow the use of offset through-hole vias (OTHVs) rather than HDI’s blind and buried vias. OTHVs place a very small via towards or at the edge of a component pad to conserve the space between pads. Taylor put in the time on the front-end design to lower the board’s manufacturing cost. Initially, Adiuvo had ten prototype boards manufactured in the UK, but manufacturing will now shift to Asia. Adiuvo hopes to have 100 Beta boards available in October, around the time that the company holds its Horizon FPGA conference in London. However, growing FPGA lead times may delay board availability. Adiuvo plans on manufacturing 3000 production boards, with production slated to start at the end of February 2027. Adiuvo is mainly in the engineering design and training business. It also runs the semiannual Horizons FPGA conference and publishes the free “FPGA Horizons Journal.” The company currently offers classes covering topics that include RTL creation, FPGA math, mixed-signal design, MicroBlaze development, and FPGA high-level synthesis. In a phone interview, Taylor told me he’s currently developing most of his code through Anthropic’s Claude and OpenAI’s ChatGPT AI assistants, so expect Adiuvo’s classes to add VHDL vibe coding as well. Over time, I expect to see the many code samples and examples already developed by Taylor and Adiuvo migrated to the new Explorer board. If you’re thinking about dipping a toe into the FPGA universe, you’d be hard-pressed to find a better bargain than this dev board. It provides low-cost access to a surprisingly powerful FPGA, and there’s a lot of existing support for the board, with more planned in the future.