Протокол AMBA CHI становится стандартом для обеспечения согласованности кэша в современных вычислительных SoC

Abstract, Cache coherency is no longer an implementation detail. A modern compute SoC carries a dozen or more coherent initiators across CPU clusters, GPU compute units, neural accelerators, and high-throughput I/O. The fabric that connects them determines how much of the SoC's nominal performance the application actually sees. AMBA CHI, the AMBA 5 Coherent Hub Interface, is the protocol the industry has converged on for that fabric. CHI is a layered, channel-segregated protocol built around a directory-based home node, designed from the start for SoC-scale coherency at hundreds of agents. Broadcast snooping does not scale beyond roughly eight coherent agents on a shared bus, and even aggressive broadcast variants stop scaling somewhere in the low hundreds of cores. Direct Memory Transfer, Direct Cache Transfer, and Direct Write Transfer remove the home node from the data path on the common case. CHI raises its own system problems in return: I/O coherency without full CHI, AXI migration, DMA address translation, off-die coherent attach, fabric-level functional safety, and topology configuration. SignatureIP's portfolio addresses these problems as one integrated system: C-NOC as the CHI coherent core, NC-NOC as the non-coherent fabric, AXI2CHI and CHI2AXI as the migration and interop bridges, Proxy Cache and ATC as the I/O-coherency and translation enablers, PCIe Controller and CXL Controller (with the pre-integrated CXL Subsystem) as the off-die attach paths, Inoculator as the cloud-based topology generator, and Ethernet IP as a representative non-coherent master. Index Terms, AMBA CHI, network-on-chip, directory-based snoop filter, DMT, DCT, DWT, RN-F, HN-F, AXI to CHI bridge, IOMMU, topology generation, PCIe 6.x, CXL 3.x, Flex Bus, multi-core SoC, CPU cluster.