ARM представила новую версию стандарта AMBA CHI C2C Issue B для масштабирования чиплетов в задачах ИИ

Learn how AMBA CHI C2C enables chiplet interoperability and scales for AI workloads through property negotiation for greater flexibility In this blog post, we introduce the Property Negotiation Learn the Architecture guide and Issue B of the AMBA CHI C2C specification, which we recently published. Chiplets and the need for standardisation Chiplets are changing how custom silicon is built. They enable performance scaling and composability. Chiplets, however, require open standards to ensure interoperability and design reuse. This reduces cost and time to market. That is why we have developed the AMBA CHI C2C specification in collaboration with industry partners. We published the first version (Issue A) in early 2024. AMBA CHI C2C extends the existing on-chip AMBA CHI protocol for connecting chip-to-chip and chiplet-to-chiplet (C2C). It builds on the success of AMBA, the open standard for SoC communications that underpins silicon IP and fabless design today. Interoperability and complexity scaling An ecosystem of reusable chiplets requires standards that enable not only interoperability and support increasing system complexity. Interoperability ensures forward and backward compatibility across product generations and between chiplets designed independently. Complexity scaling enables chiplets with different degrees of features and capabilities to connect. The use cases range from simple read/write peripherals to I/O or non-coherent device attach and fully coherent advanced heterogeneous systems. AMBA CHI C2C addresses these requirements with a property negotiation mechanism. Existing designs that use AMBA AXI can also benefit from AMBA CHI C2C through property negotiation and complexity scaling. For example, an accelerator chiplet can use properties to subset CHI to an I/O-coherent or non-coherent protocol. This subset has lower complexity and is equivalent to AMBA AXI. This enables straightforward mapping and efficient on-chip bridging. Therefore, the accelerator chiplet only needs to implement the required features, which reduces area and cost. Property negotiation has been supported since the first version of AMBA CHI C2C (Issue A). However, the new features in Issue B make forwards and backwards interoperability between generations even more important. Complexity scaling is also becoming more important with more chiplet types and AI use cases emerging. To help you understand AMBA’s approach to property negotiation, we have published the Learn the architecture – Introduction to AMBA CHI C2C property negotiation guide. Download the property negotiation introduction guide to learn more. Connecting one chiplet to various other types of chiplets with varying degrees of complexity through a single and unified interface protocol Introducing AMBA CHI C2C Issue B Since its publication, AMBA CHI C2C has gained momentum, particularly in AI applications. At the same time, AI models have evolved rapidly and increased significantly in size. As a result, performance and scalability requirements have increased, shifting the bottleneck to memory and interconnect bandwidth. We are evolving AMBA CHI C2C with Issue B (CHI-C2C-B) to address this challenge. Issue B improves bandwidth efficiency and adds features that are particularly important for chiplets and AI applications. For example: - Multi-request: Requests can target multiple cache lines, increasing efficiency due to optimized REQ message class bandwidth. - Software visible registers: Enables broader interface interoperability and re-use of standardised software for discovery and control of C2C interfaces. - Multi-hop routing: Enables support for more complex, non-fully-connected topologies. Download the AMBA CHI C2C Issue B specification to learn more.