Cadence и TSMC разрабатывают новые методики для проектирования 3D-чипов в системах искусственного интеллекта

As AI and high‑performance computing (HPC) designs advance at leading-edge nodes, design innovation is increasingly extending beyond individual dies to multi‑die and heterogeneous integration enabled by 3D‑IC technologies. However, moving beyond traditional monolithic chips requires more than advanced packaging. It requires predictable, manufacturable design methodologies that scale with system-driven complexity. In this blog, we highlight how Cadence is working with TSMC to help enable advanced AI and HPC system design through 3D-IC design using TSMC 3DFabric ® technologies (for 3D-IC design) and TSMC-COUPE TM (for photonics and high-speed interconnects), along with multiphysics analysis and signoff‑ready infrastructure. Scaling AI Beyond the Chip As AI and HPC architectures move toward chiplets and 3D-IC, the challenge is no longer just integrating more compute and memory; it is now about designing and validating a full system with confidence. As design scale increases and system requirements expand, teams must manage a broader set of interactions across dies, packages, and interconnects while still meeting performance, reliability, and signoff predictability. That challenge now extends across several dimensions: Full-stack 3D-IC closure – Coordinating dies, package, interconnect, and system interactions across repeated architecture and package iterations Multiphysics signoff complexity – Managing tightly coupled thermal, power integrity, stress/warpage, EM, and electromigration effects, with thermal closure becoming central to reliability and yield Scale and compute pressure – Handling million-plus bumps, corner explosion, signoff explosion, and large-mesh analysis without overwhelming runtime, capacity, or schedules Addressing these challenges requires more than conventional multi-die integration. It calls for a system-level, signoff-ready approach that can manage full-stack interactions, unify power and multiphysics analysis, and scale efficiently enough to keep advanced AI and HPC programs on track. This is where Cadence's collaboration with TSMC becomes especially important. Cadence has expanded its collaboration with TSMC to support the transition to multi-die architectures for AI, HPC, and client inferencing applications. The collaboration delivers signoff-ready, end-to-end design infrastructure and advanced, certified design flows for 3D-IC and leading-edge AI silicon on TSMC's N3, N2, A16 TM, and A14 process technologies. Within these flows, TSMC 3DFabric® provides the system-level foundation for 3DIC and heterogeneous integration, while TSMC Compact Universal Photonic Engine (TSMC-COUPE TM ) addresses silicon photonics and co-packaged optics for high-bandwidth optical interconnects within advanced packaging. For customers, this means fewer design iterations, better correlation across the flow, higher productivity, and a more predictable path to tapeout-quality results. These capabilities extend advanced design flows beyond individual chips to full-system integration, including chiplet assembly, packaging optimization, and system-level signal and power integrity analysis. The result is a broader design methodology that helps customers address complexity across the entire hierarchy—from die to package to interconnect to full system. Cadence 3D-IC Solution for Multi-Die and Heterogeneous Integration For 3D‑IC and heterogeneous integration, the Cadence Integrity 3D‑IC Platform and Allegro X Advanced Package Designer support a unified flow spanning system‑level planning, chiplet and package implementation, multiphysics analysis, signoff, and die‑to‑die integration. This unified approach helps align die, package, and implementation decisions earlier, which becomes increasingly important as AI systems scale in size and complexity The Cadence 3D-IC solution also supports TSMC-COUPE TM reference flows, including stacked‑die use cases, as well as silicon photonics support in the Virtuoso Heterogeneous Integration methodology. Together, these capabilities help align die, package, and implementation flows for complex multi‑die systems. Across these solution areas, the flow incorporates: System‑level planning across dies, chiplets, interposers, and package architectures Chiplet implementation, cross‑die optimization, and package co‑design Multiphysics analysis across thermal, electromagnetic, timing, power integrity, and physical verification Die‑to‑die integration and silicon photonics support for advanced heterogeneous systems Aligned with TSMC's broader 3DFabric® ecosystem and TSMC-COUPE TM reference flows, Cadence provides the enabled solutions for complex multi‑die systems and for integrating photonics for ultra-high speed and low-power interconnects. This approach connects early exploration and partitioning through implementation, package realization, analysis, verification, and die‑to‑die integration, helping customers move from architecture to tapeout with greater confidence. Multiphysics Analysis Across Thermal, Power, and Signal As AI systems scale, multiphysics effects become increasingly significant. Thermal behavior, power integrity, and signal integrity must all be analyzed together to ensure system performance and long-term reliability. As designs grow more complex, that coupled analysis becomes essential, not optional. Cadence provides a comprehensive multiphysics solution, including: Celsius Thermal Solver, for thermal analysis Voltus IC Power Integrity Solution, for power integrity analysis Clarity 3D Solver and EMX Planar 3D Solver, for electromagnetic and signal integrity analysis These capabilities enable engineers to evaluate cross‑domain interactions earlier in the design process, leading to more informed decisions and improved design outcomes before issues become expensive to correct. Aligning Analysis with Signoff Requirements In advanced 3D‑IC systems, it is not enough to perform analysis; results must align with final signoff. When early analysis and signoff diverge, the result is often costly rework, additional iterations, and schedule risk. Cadence addresses this by aligning multiphysics analysis with signoff technologies for heterogeneous systems, including the Pegasus Physical Verification Platform. This helps maintain consistency across the design flow, from early exploration to final verification, and gives engineering teams a more reliable path to closure. That alignment enables: Improved correlation between design stages Reduced late‑stage rework Greater confidence in achieving tapeout‑quality results Transition: From System Integration to AI‑Driven Design 3DIC and heterogeneous integration are helping the industry scale AI systems beyond the limits of traditional monolithic design. But as these systems grow in complexity, managing the design workflow itself becomes the defining challenge. Engineering teams must now navigate more variables, more domains, and more interactions across the full implementation and signoff path. In the next blog, we will explore how Cadence is working with TSMC to address that challenge through AI-driven, agent-ready design flows that help teams navigate growing complexity and accelerate design convergence across advanced nodes. Learn more about how we are transforming chip design with our strategic foundry partners. Cadence is a platinum sponsor of the TSMC OIP Ecosystem Forum. Visit Cadence's booth 204 and chat with our experts about the latest technologies enabling AI agents, digital full-flow, signoff, custom, and design IP solutions. Written by Vinod Khera, Lead Marketing Communications, Cadence